1. Field of the Invention
The present invention relates to a video signal processing device and a method thereof, and in particular, to a data slice circuit for separating (slicing) data carried on a video signal and a method thereof.
2. Description of the Related Art
Commonly, a broadcasting station transmits a broadcasting signal together with data for a broadcasting program service (e.g., KBPS (Korean Broadcasting Program Service), a caption service, a teletext service and an extended data service (EDS)), being carried on the video signal at a vertical blanking interval (VBI).
Receiving the broadcasting signal, a television receiver separates the data carried on the video signal at the vertical blanking interval and displays information according to the data to offer the various services mentioned above. The television receiver includes a data slice circuit for separating the data carried on the video signal at the vertical blanking interval.
Referring to FIG. 1 illustrating a conventional data slice circuit, the video signal input is applied in common to a top peak detector 10, a bottom peak detector 12, a composite synchronous signal separation circuit 16, and a non-inverse input terminal (+) of a comparator circuit 20. The top peak detector 10 detects a top peak of the video signal and generates a top peak detection signal. The bottom peak detector 12 detects a bottom peak of the video signal and generates a bottom peak detection signal. The top peak detection signal reaches an input node P of a sampling/holding circuit 14 through a resistor R1. Similarly, the bottom peak detection signal reaches the input node P of the sampling/holding circuit 14 via a resistor R2. The resistors R1 and R2 have the same resistance. Accordingly, the input node P of the sampling/holding circuit 14 has an intermediate signal between the top peak detection signal and the bottom peak detection signal. The intermediate signal (hereinafter referred to as "sampling/holding signal") is applied to the sampling/holding circuit 14.
The composite synchronous signal separation circuit 16 separates a composite synchronous signal from the input video signal. The composite synchronous signal is applied to a CRI (Clock Run In) window circuit 18. The CRI window circuit 18 generates a control signal to the sampling/holding circuit 14, in which the control signal is, for example, at a high state at a CRI interval of the composite synchronous signal, and is at a low state at the other intervals. For example, if the control signal is at the high state, the sampling/holding circuit 14 performs a sampling operation. However, in response to the control signal of the low state, the sampling/holding circuit 14 performs a holding operation.
The sampling/holding circuit 14 samples the sampling/holding signal input in response to the control signal of the high state, and holds the sampled sampling/holding signal in response to the control signal of the low state. An output signal of the sampling/holding circuit 14 becomes a reference signal.
The reference signal is applied to an inverse input terminal (-) of the comparator circuit 20. The comparator circuit 20 generates an output signal of the high state when the video signal input is higher than the reference signal, and the output signal of the low state when the video signal input is lower than the reference signal. Here, the output signal of the comparator circuit 20 becomes the data for the various services mentioned above.
In operation, the video signal shown in FIG. 2A is applied to the data slice circuit. The top peak detector 10 detects the top peak of the video signal and generates the top peak detection signal shown in FIG. 2B. The bottom peak detector 12 detects the bottom peak of the video signal and generates the bottom peak detection signal shown in FIG. 2C. The top peak detection signal and the bottom peak detection signal are applied to the input node P through the resistors R1 and R2, respectively, generating the sampling/holding signal shown in FIG. 2D. As shown in FIG. 2D, the sampling/holding signal is at an intermediate level between the top peak detection signal and the bottom peak detection signal. The sampling/holding signal is applied to the sampling/holding circuit 14.
An N-th composite synchronous signal of the video signal is separated from the video signal by the composite synchronous signal separation circuit 16 and applied to the CRI window circuit 18. The CRI window circuit 18 generates the control signal shown in FIG. 2E of the high state to cause the sampling/holding circuit 14 to perform the sampling operation only at the CRI interval on the basis of the N-th composite synchronous signal. Upon receiving the control signal of the high state, the sampling/holding circuit 14 samples the sampling/holding input signal, to generate the reference signal shown in FIG. 2F.
As the CRI interval comes to an end, the control signal is changed to the low state, responsive to which the sampling/holding circuit 14 holds the sampled sampling/holding signal. Accordingly, the sampling/holding circuit 14 generates the reference signal at a time point where the control signal is changed to the low state. The reference voltage is applied to the inverse input terminal (-) of the comparator circuit 20.
The comparator circuit 20 generates the output signal as shown in FIG. 2G of the high state when the video signal is higher than the reference voltage. The output data of the comparator circuit 20 is identical to the data carried on the video data at a data interval.
With respect to the video signal, an actual video signal is generated after the vertical synchronous signal. However, a holding interval of the sampling/holding circuit 14 continues until the actual video signal is generated. Hence, the comparator circuit 20 generates the data with respect to even the actual video signal.
However, the data generated by the actual video signal is not the data which is transmitted from the transmission party (broadcasting station) for the services mentioned above. Accordingly, the data generated by the actual video signal causes noises.
As described above, the conventional data slice circuit performs a data slice operation with respect to the video signal even at an interval other than the data interval of the video signal. As a result, the data slice circuit slices even the actual video signal, thereby generating the noises.